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w wm8706 24-bit, 192khz stereo dac with volume control wolfson microelectronics plc to receive regular email updates, sign up at http://www.wolfsonmicro.com/enews/ production data, july 2005, rev 4.1 copyright ? 2005 wolfson microelectronics plc description the wm8706 is a high performance stereo dac designed for audio applications such as dvd, home theatre systems, and digital tv. the wm8706 supports data input word lengths from 16 to 32-bits and sampling rates up to 192khz. the wm8706 can implement 2 channels at 192khz for high- end dvd-audio. the wm8706 consists of a serial interface port, digital interpolation filters, multi-bit sigma delta modulators and stereo dac in a small 28-lead ssop package. the wm8706 also includes a digitally controllable mute and attenuate function on each channel. the wm8706 supports a variety of connection schemes for audio dac control. the mpu serial port provides access to a wide range of features including on-chip mute, attenuation and phase reversal. a hardware controllable interface is also available. it is pin-compatible with the wm8716 provided the oscillator circuit on wm8716 is not required in the application. the wm8706 is an ideal device to interface to ac-3 ? , dts ? , and mpeg audio decoders for surround sound applications, or for use in dvd players supporting dvd-a. features ? stereo dac ? audio performance - 106db snr (?a? weighted @ 48khz) dac - -97db thd ? dac sampling frequency: 8khz ? 192khz ? 3-wire serial control interface or hardware control ? programmable audio data interface modes - i 2 s, left, right justified, dsp - 16/20/24/32 bit word lengths ? independent digital volume control on each channel with 127.5db range in 0.5db steps ? 3.0v ? 5.5v supply operation ? 28-lead ssop package ? exceeds dolby class a performance requirements applications ? dvd-audio and dvd ?universal? players ? home theatre systems ? digital tv ? digital broadcast receivers block diagram bckin serial interface mute/ atten control interface voutl voutr sigma delta modulator lrcin din mute/ atten sigma delta modulator digital filters xti dvdd avdd agnd dgnd muteb mddm0 mcdm1 mliis mode csbiwo zero low pass filter low pass filter vmid right dac left dac vrefn vrefp wm8706 w
wm8706 production data w pd rev 4.1 july 2005 2 table of contents description ............................................................................................................1 features..................................................................................................................1 applications ..........................................................................................................1 block diagram ......................................................................................................1 pin configuration................................................................................................3 ordering information .......................................................................................3 pin description .....................................................................................................4 absolute maximum ratings..............................................................................5 dc electrical characteristics .....................................................................6 electrical characteristics ...........................................................................6 terminology ................................................................................................................. 7 master clock timing .................................................................................................. 8 digital audio interface ............................................................................................ 8 mpu interface timing ................................................................................................. 9 device description ............................................................................................10 introduction ...............................................................................................................10 clocking schemes .....................................................................................................10 digital audio interface ...........................................................................................10 audio data sampling rates.....................................................................................13 hardware control modes .....................................................................................13 software control interface...............................................................................15 register map ...............................................................................................................16 attenuation control...............................................................................................18 digital filter characteristics ....................................................................21 dac filter responses...............................................................................................21 digital de-emphasis characteristics ........................................................22 recommended external components .......................................................23 recommended external component values ...................................................23 recommended analogue low pass filter (optional) .........................24 package dimensions .........................................................................................25 important notice ...............................................................................................26 address: ....................................................................................................................... .26
wm8706 production data w pd rev 4.1 july 2005 3 pin configuration 1 agnd 2 avdd 3 nc 4 voutl 5 vmid 6 vrefn 7 vrefp 8 mcdm1 9 zero 10 nc csbiwo mode mddm0 muteb 15 din mliis dgnd nc nc xti bckin lrcin nc nc dvdd nc nc voutr 11 12 13 14 16 17 18 19 20 21 22 23 24 25 28 27 26 ordering information device temperature range package moisture sensitivity level peak soldering temperature wm8706seds -25 to +85 o c 28-lead ssop (lead free) msl 1 260 o c wm8706seds/r -25 t o +85 o c 28-lead ssop (lead free, tape and reel) msl 1 260 o c note: reel quantity = 2,000
wm8706 production data w pd rev 4.1 july 2005 4 pin description pin name type description 1 lrcin digital input dac sample rate clock input 2 din digital input serial audio data input 3 bckin digital input audio data bit clock input. 4 nc no internal connection 5 zero digital output (open drain) infinite zero detect flag (l=izd detected, h=izd not detected) 6 nc no internal connection 7 dgnd supply digital ground supply 8 dvdd supply digital positive supply 9 nc no internal connection 10 nc no internal connection 11 nc no internal connection 12 nc no internal connection 13 voutr analogue output right channel dac output 14 agnd supply analogue ground supply 15 avdd supply analogue positive supply 16 voutl analogue output left channel dac output 17 nc no internal connection 18 vmid analogue output mid rail decoupling point 19 vrefn supply dac negative reference ? normally agnd, must not be below agnd 20 vrefp supply dac positive reference ? normally avdd, must not be above avdd 21 zero digital output infinite zero detect flag 22 nc no internal connection 23 csbiwo digital input software mode: 3-wire serial control chip select hardware mode: input word length, pull up 24 mode digital input control mode selection (low = hardware, high = software), pull down 25 muteb digital bi-directional mute control (l = mute on, h = mute off, z = automute enabled), pull up 26 mddm0 digital bi-directional software mode: 3-wire serial control data input: hardware mode: de-emphasis 27 mcdm1 digital input software mode: 3-wire serial control clock input hardware mode: de-emphasis, pull down 28 mliis digital input software mode 3-wire serial control load input hardware mode: input data format selection, pull up note: digital input pins have schmitt trigger input buffers.
wm8706 production data w pd rev 4.1 july 2005 5 absolute maximum ratings absolute maximum ratings are stress ratings only. permanent damage to the device may be caused by continuously operating at or beyond these limits. device functional operating limits and guaranteed performance specifications are given under electrical characteristics at the test conditions specified. esd sensitive device. this device is manufactured on a cmos process. it is therefore generically susceptible to damage from excessive static voltages. proper esd precautions must be taken during handling and storage of this device. wolfson tests its package types according to ipc/jedec j-std-020b for moisture sensitivity to determine acceptable storage conditions prior to surface mount assembly. these levels are: msl1 = unlimited floor life at <30 c / 85% relative humidity. not normally stored in moisture barrier bag. msl2 = out of bag storage for 1 year at <30 c / 60% relative humidity. supplied in moisture barrier bag. msl3 = out of bag storage for 168 hours at <30 c / 60% relative humidity. supplied in moisture barrier bag. the moisture sensitivity level for each package type is specified in ordering information. condition min max digital supply voltage -0.3v +7v analogue supply voltage -0.3v +7v voltage range digital inputs dgnd -0.3v dvdd +0.3v voltage range analogue inputs agnd -0.3v avdd +0.3v master clock frequency (xti) 50mhz operating temperature range, t a -25 c +85 c storage temperature -65 c +150 c note: analogue and digital grounds must always be within 0.3v of each other.
wm8706 production data w pd rev 4.1 july 2005 6 dc electrical characteristics parameter symbol test conditions min typ max unit digital supply range dvdd 3.0 5.5 v analogue supply range avdd 3.0 5.5 v ground agnd, dgnd 0 v difference dgnd to agnd -0.3 0 +0.3 v analogue supply current avdd = 5v 19 ma digital supply current dvdd = 5v 8 ma analogue supply current avdd = 3.3v 18 ma digital supply current dvdd = 3.3v 4 ma electrical characteristics test conditions avdd, dvdd = 5v, agnd, dgnd = 0v, t a = +25 o c, fs = 48khz, xti = 256fs unless otherwise stated. parameter symbol test conditions min typ max unit digital logic levels (ttl levels) input low level v il 0.8 v input high level v ih 2.0 v output low v ol i ol = 1ma agnd + 0.3v v output high v oh i oh = 1ma avdd - 0.3v v analogue reference levels reference voltage vmid (vrefp - vrefn)/2 - 50mv (vrefp - vrefn)/2 (vrefp - vrefn)2 + 50mv v potential divider resistance r vmid 10k ? dac output (load = 10k ? ? ? ? . 50pf) 0dbfs full scale output voltage at dac outputs 1.1 x avdd/5 vrms snr (note 1,2,3) a-weighted, @ fs = 48khz 100 106 db snr (note 1,2,3) a-weighted @ fs = 96khz 106 db snr (note 1,2,3) a-weighted @ fs = 192khz 106 db snr (note 1,2,3) a-weighted, @ fs = 48khz avdd, dvdd = 3.3v 102 db snr (note 1,2,3) a-weighted @ fs = 96khz avdd, dvdd = 3.3v 102 db snr (note 1,2,3) non ?a? weighted @ fs = 48khz 103 db thd (note 1,2,3) 1khz, 0dbfs -97 db thd+n (dynamic range, note 2) 1khz, -60dbfs 100 106 db dac channel separation 100 db
wm8706 production data w pd rev 4.1 july 2005 7 test conditions avdd, dvdd = 5v, agnd, dgnd = 0v, t a = +25 o c, fs = 48khz, xti = 256fs unless otherwise stated. parameter symbol test conditions min typ max unit analogue output levels load = 10k ? , 0dbfs 1.1 v rms output level load = 10k ? , 0dbfs, (avdd = 3.3v) 0.726 v rms gain mismatch channel-to-channel 1 %fsr to midrail or a.c. coupled 1 k ? minimum resistance load to midrail or a.c. coupled (avdd = 3.3v) 600 ? maximum capacitance load 5v or 3.3v 100 pf output d.c. level (vrefp - vrefn)/2 v power on reset (por) por threshold 2.4 v notes: 1. ratio of output level with 1khz full scale input, to the output level with all zeros into the digital input, measured ?a? we ighted over a 20hz to 20khz bandwidth. 2. all performance measurements done with 20khz low pass filter, and where noted an a-weight filter. failure to use such a filter will result in higher thd+n and lower snr and dynamic range readings than are found in the electrical characteristics. the low pass filter removes out of band noise; although it is not audible it may affect dynamic specification values. 3. vmid decoupled with 10uf and 0.1uf capacitors (smaller values may result in reduced performance). terminology 1. signal-to-noise ratio (db) - snr is a measure of the difference in level between the full scale output and the output with n o signal applied. (no auto-zero or automute function is employed in achieving these results). 2. dynamic range (db) - dnr is a measure of the difference between the highest and lowest portions of a signal. normally a thd+n measurement at 60db below full scale. the measured signal is then corrected by adding the 60db to it. (e.g. thd+n @ -60db= -32db, dr= 92db). 3. thd+n (db) - thd+n is a ratio, of the rms values, of (noise + distortion)/signal. 4. stop band attenuation (db) - is the degree to which the frequency spectrum is attenuated (outside audio band). 5. channel separation (db) - also known as cross-talk. this is a measure of the amount one channel is isolated from the other. normally measured by sending a full scale signal down one channel and measuring the other.
wm8706 production data w pd rev 4.1 july 2005 8 master clock timing xti t xtil t xtih t xtiy figure 1 master clock timing requirements test conditions avdd, dvdd = 5v, agnd, dgnd = 0v, t a = +25 o c, fs = 48khz, xti = 256fs unless otherwise stated. parameter symbol test conditions min typ max unit master clock timing information xti master clock pulse width high t xtih 13 ns xti master clock pulse width low t xtil 13 ns xti master clock cycle time t xtiy 26 ns xti duty cycle 40:60 60:40 digital audio interface bckin lrcin t bch t bcl t bcy din t lrsu t ds t lrh t dh figure 2 digital audio data timing test conditions avdd, dvdd = 5v, agnd, dgnd = 0v, t a = +25 o c, fs = 48khz, xti = 256fs unless otherwise stated. parameter symbol test conditions min typ max unit audio data input timing information bckin cycle time t bcy 40 ns bckin pulse width high t bch 16 ns bckin pulse width low t bcl 16 ns lrcin set-up time to bckin rising edge t lrsu 8 ns lrcin hold time from bckin rising edge t lrh 8 ns din set-up time to bckin rising edge t ds 8 ns din hold time from bckin rising edge t dh 8 ns
wm8706 production data w pd rev 4.1 july 2005 9 mpu interface timing mliis mcdm1 mddm0 t csl t dho t dsu t csh t scy t sch t scl t scs lsb t css csbiwo t cssh t cssu figure 3 program register input timing - 3-wire serial control mode test conditions avdd, dvdd = 5v, agnd, dgnd = 0v, t a = +25 o c, fs = 48khz, xti = 256fs unless otherwise stated. parameter symbol test conditions min typ max unit program register input information mcdm1 rising edge to mliis rising edge t scs 40 ns mcdm1 pulse cycle time t scy 80 ns mcdm1 pulse width low t scl 20 ns mcdm1 pulse width high t sch 20 ns mddm0 to mcdm1 set-up time t dsu 20 ns mcdm1 to mddm0 hold time t dho 20 ns mliis pulse width low t csl 20 ns mliis pulse width high t csh 20 ns mliis rising to sclk rising t css 20 ns csbiwo to mliis set-up time t cssu 20 ns mliis to csbiwo hold time t cssh 20 ns
wm8706 production data w pd rev 4.1 july 2005 10 device description introduction the wm8706 is a high performance dac designed for digital consumer audio applications. its range of features make it ideally suited for use in dvd players, av receivers and other high end consumer audio equipment. the wm8706 is a complete 2-channel stereo audio digital-to-analogue converter, including digital interpolation filter, multi-bit sigma delta with dither, and switched capacitor multi-bit stereo dac and output smoothing filters. the wm8706 includes an on-board digital volume control, configurable digital audio interface and a 3 wire mpu control interface. it is fully compatible and an ideal partner for a range of industry standard microprocessors, controllers and dsps. control of internal functionality of the device is by either hardware control (pin programmed) or software control (3-wire serial control interface). the mode pin selects between hardware and software control. the software control interface may be asynchronous to the audio data interface. control data will be re-synchronised to the audio processing internally. operation using master clocks of 256fs, 384fs, 512fs or 768fs is provided, selection between clock rates being automatically controlled in hardware mode, or serial controlled when in software mode. sample rates (fs) from less than 8ks/s to 96ks/s are allowed, provided the appropriate master clock is input. support is also provided for up to 192ks/s using a master clock of 128fs or 192fs. the audio data interface supports right, left and i 2 s (philips left justified, one bit delayed) interface formats along with a highly flexible dsp serial port interface. when in hardware mode, the three serial interface pins become control pins to allow selection of input data format type (i 2 s or right justified), input word length (16, 20, or 24-bit) and de-emphasis functions. the device is packaged in a small 28-pin ssop and is a pin-compatible alternative to the wm8716. clocking schemes in a typical digital audio system there is only one central clock source producing a reference clock to which all audio data processing is synchronised. this clock is often referred to as the audio system?s master clock. the external master system clock can be applied directly through the xti input pin with no software configuration necessary for sample rate selection. note that on the wm8706, xti is used to derive clocks for the dac path. the dac path consists of dac sampling clock, dac digital filter clock and dac digital audio interface timing. in a system where there are a number of possible sources for the reference clock it is recommended that the clock source with the lowest jitter be used to optimise the performance of the dac. digital audio interface audio data is applied to the internal dac filters via the digital audio interface. 5 popular interface formats are supported: ? left justified mode ? right justified mode ? i 2 s mode ? dsp early mode ? dsp late mode all 5 formats send the msb first and support word lengths of 16, 20, 24 and 32 bits. the exception is that 32 bit data is not supported in right justified mode. din and lrcin are sampled on the rising, or falling edge of bckin depending on the format selected. in left justified, right justified and i 2 s modes, the digital audio interface receives data on the din input. audio data is time multiplexed with lrcin indicating whether the left or right channel is present. lrcin is also used as a timing reference to indicate the beginning or end of the data words.
wm8706 production data w pd rev 4.1 july 2005 11 in left justified, right justified and i 2 s modes, the minimum number of bckins per lrcin period is 2 times the selected word length. lrcin must be high for a minimum of word length bckins and low for a minimum of word length bckins. any mark to space ratio on lrcin is acceptable provided the above requirements are met. the wm8706 will automatically detect when data with a lrcin period of exactly 32 is sent, and select 16 bit mode - overriding any previously programmed word length. word length will revert to the previously programmed value when a lrcin period other than 32 is detected. (see figure 4, figure 5 and figure 6). in dsp early or dsp late mode, the data is time multiplexed onto din. lrcin is used as a frame sync signal to identify the msb of the first word. the minimum number of bckins per lrcin period is 2 times the selected word length. any mark to space ratio is acceptable on lrcin provided the rising edge is correctly positioned (see figure 7 and figure 8). left justified mode in left justified mode, the msb is sampled on the first rising edge of bckin following a lrcin transition. lrcin is high during the left samples and low during the right samples. left channel right channel lrcin bckin din 1/fs n 3 2 1 n-2 n-1 lsb msb n 3 2 1 n-2 n-1 lsb msb figure 4 left justified mode timing diagram right justified mode in right justified mode, the lsb is sampled on the rising edge of bckin preceding a lrcin transition. lrcin is high during the left samples and low during the right samples. left channel right channel lrcin bckin din 1/fs n 3 2 1 n-2 n-1 lsb msb n 3 2 1 n-2 n-1 lsb msb figure 5 right justified mode timing diagram
wm8706 production data w pd rev 4.1 july 2005 12 i 2 s mode in i 2 s mode, the msb is sampled on the second rising edge of bckin following a lrcin transition. lrcin is low during the left samples and high during the right samples. left channel right channel lrcin bckin din 1/fs n 3 2 1 n-2 n-1 lsb msb n 3 2 1 n-2 n-1 lsb msb 1 bckin 1 bckin figure 6 i 2 s mode timing diagram dsp early mode in dsp early mode, the first bit is sampled on the bckin rising edge following the one which detects a low to high transition on lrcin. no bckin edges are allowed between the data words. the word order is din left, din right. lrcin bckin din input word length (iwo) 1/fs left channel n 2 1 n-1 lsb msb n 2 1 n-1 right channel no valid data 1 bckin 1 bckin figure 7 dsp early mode timing diagram dsp late mode in dsp late mode, the first bit is sampled on the bckin rising edge which detects a low to high transition on lrcin. no bckin edges are allowed between the data words. the word order is din left, din right. lrcin bckin din input word length (iwo) 1/fs left channel n 2 1 n-1 lsb msb n 2 1 n-1 right channel no valid data 1 figure 8 dsp late mode timing diagram
wm8706 production data w pd rev 4.1 july 2005 13 audio data sampling rates the master clock for wm8706 supports audio sampling rates from 128fs to 768fs, where fs is the audio sampling frequency (lrcin) typically 32khz, 44.1khz, 48khz, 96khz or 192khz. the master clock is used to operate the digital filters and the noise shaping circuits. the wm8706 has a master clock detection circuit that automatically determines the relation between the master clock frequency and the sampling rate (to within +/- 32 master clocks). if there is a greater than 8 clocks error, the interface shuts down the dac and mutes the output. the master clock should be synchronised with lrcin, although the wm8706 is tolerant of phase differences or jitter on this clock. master clock frequency (mhz) (xti) sampling rate (lrcin) 128fs 192fs 256fs 384fs 512fs 768fs 32khz 4.096 6.144 8.192 12.288 16.384 24.576 44.1khz 5.6448 8.467 11.2896 16.9340 22.5792 33.8688 48khz 6.114 9.216 12.288 18.432 24.576 36.864 96khz 12.288 18.432 24.576 36.864 unavailable unavailable 192khz 24.576 36.864 unavailable unavailable unavailable unavailable table 1 typical relationships between system frequency and sampling rates. hardware control modes when the mode pin is held low, the following hardware modes of operation are available. mute and automute operation in both hardware and software modes, pin 25 (muteb) controls selection of mute directly, and can be used to enable and disable the automute function. automute is enabled by leaving muteb pin floating, it is disabled by applying a signal to the pin. when left floating this pin becomes an output and indicates infinite zero detect (izd), see also pin 5 (zero). the status of izd controls the selection of mute when automute is enabled. when izd is detected mute is enabled and when izd is not detected mute is disabled. muteb pin description 0 mute dac channels 1 normal operation floating enable izd, muteb becomes an output to indicate when izd occurs. table 2 mute and automute control zero pin description 0 indicates infinite zero detected from the digital input. 1 indicates infinite zero not detected from the digital input. table 3 zero pin output
wm8706 production data w pd rev 4.1 july 2005 14 figure 9 shows the application and release of mute whilst a full amplitude sinusoid is being played at 48khz sampling rate. when mute (lower trace) is asserted, the output (upper trace) begins to decay exponentially from the dc level of the last input sample. the output will decay towards v mid with a time constant of approximately 64 input samples. when mute is de- asserted, the output will restart almost immediately from the current input sample. -2.5 -2 -1.5 -1 -0.5 0 0.5 1 1.5 0 0.001 0.002 0.003 0.004 0.005 0.006 time(s) figure 9 application and release of soft mute the muteb pin is an input to select mute or not mute. muteb is active low; taking the pin low causes the filters to soft mute, ramping down the audio signal over a few milliseconds. taking muteb high again allows data into the filter. the automute function detects a series of zero value audio samples of 1024 samples long being applied to both channels. after such an event, a latch is set whose output (automuted) is wire or?ed through a 10kohm resistor to the muteb pin. thus if the muteb pin is not being driven, the automute function will assert mute. if muteb is tied high, automute is overridden and will not mute unless the izd register bit is set. if muteb is driven from a bi-directional source, then both mute and automute functions are available. if muteb is not driven, automuted appears as a weak output (10k source impedance) so can be used to drive external mute circuits. automute will be removed as soon as any channel receives a non-zero input. a diagram showing how the various mute modes interact is shown below in figure 10. izd (register bit) automuted (internal signal) 10k ? ? ? ? mut (register bit) softmute (internal signal) muteb pin figure 10 selection logic for mute modes
wm8706 production data w pd rev 4.1 july 2005 15 input format selection in hardware mode, mliis (pin 28) and csbiwo (pin 23) become input controls for selection of input data format type and input data word length. mliis csbiwo input data mode 0 0 24-bit right justified** 0 1 20-bit right justified 1 0 16-bit i 2 s 1 1 24-bit i 2 s table 4 input format selection note: in 24 bit i 2 s mode, any width of 24 bits or less is supported provided that lrcin is high for a minimum of 24 bckins and low for a minimum of 24 bckins. ** this mode differs from the wm8716 which does 16-bit right justified in this mode. the previous mode is still available by using exactly 32 bckin per lrcin cycle, 16 for left and right. this mode is automatically detected within the hardware and overrides the data width specified but not the format. de-emphasis control in hardware mode, mcdm1 (pin 27) and mddm0 (pin 26) become input controls for selection of de-emphasis filtering to be applied. mcdm1 mddm0 de-emphasis** 0 0 off 0 1 48khz 1 0 44.1khz 1 1 32khz table 5 de-emphasis control note: ** the actual de-emphasis within the wm8706 is the same for all data rates. this differs from wm8716 which has a different response for each sample rate. software control interface selection of control mode the wm8706 may be programmed to operate in hardware or software control modes. this is achieved by setting the state of the mode pin. mode interface format 0 hardware control mode 1 software control mode table 6 control interface mode selection
wm8706 production data w pd rev 4.1 july 2005 16 3-wire (spi compatible) serial control mode the wm8706 can be controlled using a 3-wire serial interface. mddm0 is used for the program data, mcdm1 is used to clock in the program data and mliis is used to latch in the program data. the 3-wire interface protocol is shown in figure 11. mliis mcdm1 mddm0 b15 b6 b7 b8 b9 b10 b11 b12 b13 b14 b1 b2 b3 b4 b5 b0 figure 11 3-wire serial interface notes : 1. b[15:9] are control address bits 2. b[8:0] are control data bits register map wm8706 uses a total of 4 programme registers, which are 16-bits long. these registers are all loaded through input pin mddm0. after the 16 data bits are clocked in, mliis is used to latch in the data to the appropriate register. table 7 shows the complete mapping of the 4 registers. b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 m0 0 0 0 0 0 0 0 updatel lat7 lat6 lat5 lat4 lat3 lat2 lat1 lat0 m1 0 0 0 0 0 0 1 updater rat7 rat6 rat5 rat4 rat3 rat2 rat1 rat0 m2 0 0 0 0 0 1 0 0 0 0 iw2 iw1 iw0 pwrdn deemph mut m3 0 0 0 0 0 1 1 izd sf1 sf0 bcp rev 0 atc lrp i 2 s address data table 7 mapping of program registers
wm8706 production data w pd rev 4.1 july 2005 17 register address a2, a1, a0 bits label default description [7:0] lat[7:0] 11111111 (0db) attenuation data for left channel in 0.5db steps. 000 a2, a1, a0 dacl attenuation 8 updatel 0 attenuation data load control for left channel. 0: store dacl in intermediate latch (no change to output) 1: store dacl and update attenuation on all channels. [7:0] rat[7:0] 11111111 (0db) attenuation data for right channel in 0.5db steps. 001 dacr attenuation 8 updater 0 attenuation data load control for right channel. 0: store dacr in intermediate latch (no change to output) 1: store dacr and update attenuation on all channels. 0 mut 0 left and right dacs soft mute control. 0: no mute 1: mute 1 deemph 0 de-emphasis control. 0: de-emphasis off 1: de-emphasis on 2 pwdn 0 left and right dacs power-down control 0: all dacs running, output is active 1: all dacs in power saving mode, output muted 010 dac control [5:3] iw[2:0] 000 audio data format select. 0 i 2 s 0 audio data format select. 1 lrp 0 polarity select for lrcin/dsp mode select. 0: normal lrcin polarity/dsp late mode 1: inverted lrcin polarity/dsp early mode 2 atc 0 attenuator control. 0: all dacs use attenuations as programmed. 1: right channel dacs use corresponding left dac attenuations 4 rev 0 output phase reverse. 5 bcp 0 bckin polarity 0 : normal bckin polarity 1: inverted bckin polarity [7:6] sf[1:0] 00 de-emphasis sample rate select. 011 interface control 8 izd 0 infinite zero detection circuit control and automute control 0: infinite zero detect disabled 1: infinite zero detect enabled table 8 register bit descriptions
wm8706 production data w pd rev 4.1 july 2005 18 attenuation control each dac channel can be attenuated digitally before being applied to the digital filter. attenuation is 0db by default but can be set between 0 and 127.5db in 0.5db steps using the 8 attenuation control bits. all attenuation registers are double latched allowing new values to be pre-latched to both channels before being updated synchronously. setting the update bit on any attenuation write will cause all pre-latched values to be immediately applied to the dac channels. register address a2, a1, a0 bit label default description 7:0 lat[7:0] 11111111 (0db) attenuation data for left channel dacl in 0.5db steps. 000 dacl attenuation 8 updatel 0 controls simultaneous update of all attenuation latches 0: store dacl in intermediate latch (no change to output) 1: store dacl and update attenuation on all channels. 7:0 rat[7:0] 11111111 (0db) attenuation data for right channel dacr in 0.5db steps. 001 dacr attenuation 8 updater 0 controls simultaneous update of all attenuation latches 0: store dacr in intermediate latch (no change to output) 1: store dacr and update attenuation on all channels. table 9 attenuation register map note: 1. the update bit is not latched. if update=0, the attenuation value will be written to the pre-latch but not applied to the relevant dac. if update=1, all pre-latched values will be applied from the next input sample. 2. care should be used in reducing the attenuation as rapid large volume changes can introduce zipper noise. dac output attenuation registers lat and rat control the left and right channel attenuation. table 10 shows how the attenuation levels are selected from the 8-bit words. xat[7:0] attenuation level 00(hex) db (mute) 01(hex) 127.5db : : : : : : fe(hex) 0.5db ff(hex) 0db table 10 attenuation control levels mute modes setting the mut register bit will apply a 'soft' mute to the input of the digital filters: register address bit label default description 010 dac control 0 mut 0 soft mute select 0 : normal operation 1: soft mute all channels table 11 mute control de-emphasis mode setting the deemph register bit puts the all the digital filters into de-emphasis mode: register address bit label default description 010 dac control 1 deemph 0 de-emphasis mode select: 0 : de-emphasis off 1: de-emphasis on table 12 de-emphasis control
wm8706 production data w pd rev 4.1 july 2005 19 powerdown mode setting the pwdn register bit immediately connects all outputs to v mid and selects a low power mode. all trace of the previous input samples is removed, and all register settings are cleared. when pwdn is cleared again the first 16 input samples will be ignored as the fir will repeat it's power-on initialisation sequence. register address bit label default description 010 dac control 2 pwdn 0 power down mode select: 0 : normal mode 1: power down mode table 13 powerdown control digital audio interface control registers the wm8706 has a fully featured digital audio interface that is a superset of that contained in the wm8716. interface format is selected via the iw[2:0] register bits in register m2 and the i 2 s register bit in m3. register address bit label default description 010 dac control 5:3 iw[2:0] 000 interface format select table 14 interface format controls register address bit label default description 011 interface control 0 i 2 s 0 interface format select table 15 interface format control iw2 i 2 s iw1 iw0 audio interface description ** 0 0 0 0 16 bit right justified mode 0 0 0 1 20 bit right justified mode 0 0 1 0 24 bit right justified mode 0 0 1 1 24 bit left justified mode 0 1 0 0 16 bit i 2 s mode 0 1 0 1 24 bit i 2 s mode 0 1 1 0 20 bit i 2 s mode 0 1 1 1 20 bit left justified (msb first) mode 1 0 0 0 16 bit dsp mode 1 0 0 1 20 bit dsp mode 1 0 1 0 24 bit dsp mode 1 0 1 1 32 bit dsp mode 1 1 0 0 16 bit left justified mode table 16 audio data input format note: ** in all modes, the data is signed 2's complement. the digital filters always input 24-bit data. if the dac is programmed to receive 16 or 20 bit data, the wm8706 pads the unused lsbs with zeros. if the dac is programmed into 32 bit mode, the 4 lsbs are ignored. selection of lrcin polarity in left justified, right justified or i 2 s modes, the lrp register bit controls the polarity of lrcin. if this bit is set high, the expected polarity of lrcin will be the opposite of that shown in figure 4, figure 5 and figure 6. note that if this feature is used as a means of swapping the left and right channels, a 1 sample phase difference will be introduced. register address bit label default description 011 interface control 1 lrp 0 lrcin polarity (normal) 0 : normal lrcin polarity 1: inverted lrcin polarity table 17 lrcin polarity control
wm8706 production data w pd rev 4.1 july 2005 20 in dsp modes, the lrcin register bit is used to select between early and late modes: register address bit label default description 011 interface control 1 lrp 0 dsp format (dsp modes) 0 : early dsp mode 1: late dsp mode table 18 dsp format control in dsp early mode, the first bit is sampled on the bckin rising edge following the one that detects a low to high transition on lrcin. in dsp late mode, the first bit is sampled on the bckin edge, which detects a low to high transition on lrcin. no bckin rising edges are allowed between the data words. the word order is din left, din right. attenuator control mode setting the atc register bit causes the left channel attenuation settings to be applied to both left and right channel dacs from the next audio input sample. no update to the attenuation registers is required for atc to take effect. register address bit label default description 011 interface control 2 atc 0 attenuate control mode: 0 : right channels use right attenuation 1: right channels use left attenuation table 19 attenuation control select output phase reversal the rev register bit controls the phase of the output signal. setting the rev bit causes the phase of the output signal to be inverted. register address bit label default description 011 interface control 4 rev 0 analogue output phase 0: normal 1: inverted table 20 output phase control bckin polarity by default, lrcin and din are sampled on the rising edge of bckin and should ideally change on the falling edge. data sources which change lrcin and din on the rising edge of bckin can be supported by setting the bcp register bit. setting bcp to 1 inverts the polarity of bckin to the inverse of that shown in figure 4, figure 5, figure 6, figure 7 and figure 8. register address bit label default description 011 interface control 5 bcp 0 bckin polarity 0 : normal bckin polarity 1: inverted bckin polarity table 21 bckin polarity control de-emphasis sample rate selection the sf[1:0] bits are used to select the de-emphasis rate. register address bit label default description ** 0011 interface control 7:6 sf[1:0] 00 de-emphasis sample rate selection 00 : de-emphasis off 01: 48khz 10: 44.1khz 11: 32khz table 22 de-emphasis control note: ** there is only one internal de-emphasis mode optimised for 44.1khz. this is in contrast to wm8716 which is individually optimised for each sample rate.
wm8706 production data w pd rev 4.1 july 2005 21 infinite zero detection setting the izd register bit determines whether the device is automuted when a sequence of more than 1024 zeros is detected. register address bit label default description 011 interface control 8 izd 0 infinite zero detection circuit control and automute control 0: infinite zero detect disabled 1: infinite zero detect enabled table 23 izd control digital filter characteristics parameter symbol test conditions min typ max unit passband edge -3db 0.487fs passband ripple f < 0.444fs 0.05 db stopband attenuation f > 0.555fs -60 db table 24 digital filter characteristics dac filter responses -120 -100 -80 -60 -40 -20 0 0 0.5 1 1.5 2 2.5 3 response (db) frequency (fs) figure 12 dac digital filter frequency response - 44.1, 48 and 96khz -0.2 -0.15 -0.1 -0.05 0 0.05 0.1 0.15 0.2 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 response (db) frequency (fs) figure 13 dac digital filter ripple - 44.1, 48 and 96khz -80 -60 -40 -20 0 0 0.2 0.4 0.6 0.8 1 response (db) frequency (fs) figure 14 dac digital filter frequency response - 192khz -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 response (db) frequency (fs) figure 15 dac digital filter ripple - 192khz
wm8706 production data w pd rev 4.1 july 2005 22 digital de-emphasis characteristics -10 -8 -6 -4 -2 0 0 2 4 6 8 10 12 14 16 response (db) frequency (khz) figure 16 de-emphasis frequency response (32khz) -3 -2.5 -2 -1.5 -1 -0.5 0 0.5 1 0 2 4 6 8 10 12 14 16 response (db) frequency (khz) figure 17 de-emphasis error (32khz) -10 -8 -6 -4 -2 0 0 5 10 15 20 response (db) frequency (khz) figure 18 de-emphasis frequency response (44.1khz) -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0 5 10 15 20 response (db) frequency (khz) figure 19 de-emphasis error (44.1khz) -10 -8 -6 -4 -2 0 0 5 10 15 20 response (db) frequency (khz) figure 20 de-emphasis frequency response (48khz) -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 0 5 10 15 20 response (db) frequency (khz) figure 21 de-emphasis error (48khz)
wm8706 production data w pd rev 4.1 july 2005 23 recommended external components figure 22 external components diagram recommended external component values component reference suggested value description c1 and c5 10 f de-coupling for dvdd and avdd/vrefp c2 to c4 0.1 f de-coupling for dvdd and avdd/vrefp c6 and c7 10 f output ac coupling caps to remove midrail dc level from outputs. c8 0.1 f c9 10 f reference de-coupling capacitors for vmid pin. c10 10f filtering for vrefp. omit if avdd low noise. r1 10k ? 10k pull-up to dvdd. r2 33 ? filtering for vrep. use 0 ? if avdd low noise. table 25 external components description
wm8706 production data w pd rev 4.1 july 2005 24 recommended analogue low pass filter (optional) + _ + +vs -vs 10uf 51 ? 7.5k ? 680pf 1.8k ? 47k ? 4.7k ? 4.7k ? 1.0nf figure 23 recommended low pass filter (optional)
wm8706 production data w pd rev 4.1 july 2005 25 package dimensions notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. body dimensions do not include mold flash or protrusion, not to exceed 0.20mm. d. meets jedec.95 mo-150, variation = ah. refer to this specification for further details. dm007.d ds: 28 pin ssop (10.2 x 5.3 x 1.75 mm) symbols dimensions (mm) min nom max a ----- ----- 2.0 a 1 0.05 ----- 0.25 a 2 1.65 1.75 1.85 b 0.22 0.30 0.38 c 0.09 ----- 0.25 d 9.90 10.20 10.50 e e 7.40 7.80 8.20 5.00 5.30 5.60 l 0.55 0.75 0.95 a a2 a1 14 1 15 28 e1 e c l gauge plane 0.25 e b d seating plane -c- 0.10 c ref: jedec.95, mo-150 e 1 l 1 0.125 ref 0.65 bsc l 1 0 o 4 o 8 o
wm8706 production data w pd rev 4.1 july 2005 26 important notice wolfson microelectronics plc (wm) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, tha t information being relied on is current. all products are sold subject to the wm terms and conditions of sale supplied at the ti me of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. wm warrants performance of its products to the specifications applicable at the time of sale in accordance with wm?s standard warranty. testing and other quality control techniques are utilised to the extent wm deems necessary to support this warranty. specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. in order to minimise risks associated with customer applications, adequate design and operating safeguards must be used by the customer to minimise inherent or procedural hazards. wolfson products are not authorised for use as critical components in life support devices or systems without the express written approval of an officer of the company. life support devices or systems are devices or systems that are intended for surgical implant into the body, or support or sustain life, and whose fail ure to perform when properly used in accordance with instructions for use provided, can be reasonably expected to result in a significant injury to the user. a critical component is any component of a life support device or system whose failure to perfo rm can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. wm assumes no liability for applications assistance or customer product design. wm does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual proper ty right of wm covering or relating to any combination, machine, or process in which such products or services might be or are used. wm?s publication of information regarding any third party?s products or services does not constitute wm?s approval, license, warranty or endorsement thereof. reproduction of information from the wm web site or datasheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations and notices. representation or reproduction of this informati on with alteration voids all warranties provided for an associated wm product or service, is an unfair and deceptive business practice, and wm is not responsible nor liable for any such use. resale of wm?s products or services with statements different from or beyond the parameters stated by wm for that product or service voids all express and any implied warranties for the associated wm product or service, is an unfair and deceptive business practice, and wm is not responsible nor liable for any such use. address: wolfson microelectronics plc 26 westfield road edinburgh eh11 2qb united kingdom tel :: +44 (0)131 272 7000 fax :: +44 (0)131 272 7001 email :: sales@wolfsonmicro.com

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